The present invention generally relates to multiplexer control systems, and more particularly to a multiplexer control system for multiplexing data of a plurality of channels including channels having different transmission speeds.
Various known multiplexing methods such as bit multiplexing or byte multiplexing are employed to multiplex data of a plurality of channels. When multiplexing data of channels having different transmission speeds, data of channels having higher transmission speeds are more frequently multiplexed than data of channels having lower transmission speeds. There are demands to economically realize a construction capable of multiplexing data on channels having different transmission speeds.
FIG. 1 shows a conventional construction adapted for multiplexing data on channels having different transmission speeds, in which a multiplexer 51, a channel specifying part 52, a selector 53, an output timing signal generating circuit 54, a frequency dividing circuit 55 and a basic clock generating circuit 56 are provided. The basic clock generated by the basic clock generating circuit 56 is frequency divided by the frequency dividing circuit 55. Based on the frequency divided output signal, the output timing signal generating circuit 54 generates output timing signals depending on the transmission speeds of channels CH1 through CHn.
The channel specifying part 52 supplies a channel specifying signal for specifying the channels CH1 through CHn to the selector 53 and the multiplexer 51. The selector 53 selects an output timing signal depending on the channel specifying signal and outputs. the selected output timing signal to the multiplexer 51. The multiplexer 51 selects the data of the channels CH1 through CHn specified by the channel specifying signal and multiplexes the selected data depending on the output timing signal. In this way, it is possible to multiplex data of a plurality of channels including channels having different transmission speeds.
In case the transmission speed of the channels CH1 through CHn is to be changed, it can be dealt with by modifying the construction of the selector 53 so as to change the corresponding relationship between the channel specifying signals and the output timing signals. The addition or deletion of a channel is dealt with by changing the channel specifying signal output from the channel specifying part 52. There is also a known construction wherein the selector 53 is omitted, and the output timing signals corresponding to the transmission speeds of the channels CH1 through CHn are distributed to the respective channels CH1 through CHn.
The asynchronous transfer mode (ATM) makes transmission in units of a 53 byte fixed length cell made up of a 5-byte header portion and a 48-byte data portion. The cells of the channels CH1 through CHn are multiplexed by the multiplexer 51 depending on the respective transmission speeds of the channels CH1 through CHn. The cells of a plurality of channels, including channels having different transmission speeds, are multiplexed so that cells of a channel having a higher transmission speed are multiplexed more frequently than cells of a channel having a lower transmission speed.
In the above described cell multiplexing, the output timing signal generating circuit 54 generates an output timing signal indicating the transmission timing of the cell in correspondence with the transmission speed. The period of the output timing signals for the channels having a high transmission speed is short, and the period of the timing signals for the channels having a low transmission speed is long.
In the conventional multiplexer control system for multiplexing data of a plurality of channels including channels having different transmission speeds, the output timing signal generating circuit 54 generates the output timing signal corresponding to the transmission speed based on a signal which is obtained by frequency dividing the basic clock signal by the frequency dividing circuit 55. Hence, there is a drawback in that as the number of channels and the number of kinds of transmission speeds increase, the circuit scale of the frequency dividing circuit 55 and the output timing signal generating circuit 54 becomes large. In addition, the number of the interconnecting wirings becomes large, resulting in an increase in the cost of the system.